This invention relates to the field of semiconductor integrated circuits, particularly to circuits useful for generating local clock signals synchronized to an external reference clock, and to semiconductor memory devices with such circuits.
System specifications for double data rate dynamic random access memory(DDR DRAM) require the device in a read cycle to switch its data lines(DQ) coincident with transitions of an externally generated reference clock. The fact that the frequency of the reference clock is not known precisely presents an obstacle to meeting the above requirement. The fact that the DQ line drivers have significant delays presents another obstacle.
To meet the above requirement, a DDR DRAM device typically employs a delay locked loop(DLL) to create a delayed replica clock that exactly matches the system reference clock in both frequency and phase. The DLL creates its replica clock by making a delayed copy of the reference clock. The copy has the same frequency as the reference clock because delaying a signal does not change its frequency. The DLL adjusts the delay of the copy until the copy is delayed by one or more full clock cycles from the reference clock. At this point, the reference clock and the delayed copy of the reference clock are synchronized, and the copy is then a replica of the reference clock.
The following discussion describes the DLL as locked when its replica clock matches the frequency and phase of the reference clock, and describes the smallest available delay increment by which the DLL may be adjusted as the resolution of the DLL.
The DLL typically taps a DQ clock signal from its delay signal path at a point preceding the replica clock by one clock input buffer delay, plus a DQ line driver delay(buffer delay). The phase of the DQ clock therefore leads the phase of the replica clock by one buffer delay. When the DLL is locked, the phase of the DQ clock signal also leads the reference clock by one buffer delay. The DQ clock may be used to trigger the DQ line drivers so that the DQ lines switch coincident with the reference clock transitions, thus meeting the above requirement.
The speed with which a DLL can achieve the locked condition is an important aspect of DLL performance. At system startup, after every self-refresh, and after exiting low power modes, a DLL which locks more quickly than other designs can perform its first read sooner, improving overall performance of the device.
The stability of the DLL locking in the presence of normal electrical disturbances is another important aspect of DLL performance. A design which loses lock due to a change in supply voltage or temperature cannot function until lock is regained.
FIG. 1 shows prior art in delay locked loops as summarized in Keeth and Baker, ‘DRAM Circuit Design, A Tutorial,’ IEEE Press, New York, 2001, page 143. In FIG. 1, a shift register 120 selects the number of delay increments applied by a delay line 110 to an external reference clock 102. Delayed clock 130 emerging from the delay line triggers output data 160, data strobe 170, and feeds back to phase detector 150 through delay block 140. Delay block 140 replicates the delay of input buffer 104. Phase detector 150 controls shift register 120 to remove any phase difference between its input signals 106 and 146 that are larger than the incremental delays controlled by its counter, as known by one skilled in the art.
The FIG. 1 design uses a single delay line having the same unit delay in each stage. This approach has the disadvantage of requiring many delay stages to do its job. As a typical example, if the maximum clock period is 10 nanoseconds, and the minimum clock period is 5 nanoseconds, and the delay resolution is 100 picoseconds, the FIG. 1 design requires 50 delay stages to meet the requirements with no margin. Implementing such a large number of stages requires more device size and power consumption than necessary.
The large number of stages also causes the disadvantage of slow locking. The phase detector must wait at least two clock cycles before making each decision, and each decision can only adjust total delay by a single unit delay. Thus the design of FIG. 1 moves toward locking by taking small steps, often over many steps.
The design of FIG. 1 has the further disadvantage of making delay adjustments by varying the location where the clock signal enters the delay line, so the adjustments propagate through all active delay elements before evaluation at the phase detector. Adjusting at the beginning end, rather than the trailing end, of the delay line slows evaluation of the adjustment, because the design has to wait before evaluating until each adjustment propagates to the phase detector. The design must address the worst case, and pause before evaluating for the full length of the delay line.
The FIG. 1 design has a further disadvantage of requiring flip-flops in the shift register outputs that control the delay line. Because the design needs flip-flops with near-zero setup time, the design operates the flip-flops close to the region where metastable operation can occur. For reliable flip-flop performance, the design must add either extra filtering circuitry, or extra setup delay. The use of flip-flops causes the device to suffer extra size or reduced performance.
FIG. 2 shows further prior art, U.S. Pat. No. 6,438,067, issued Aug. 20, 2002 to Kuge et al. This patent teaches a DLL having an adjustable delay buffer and an adjustable delay line in series. Delay elements in the delay buffer provide delay increments that are smaller than those in the delay line. Reference clock 202 enters a delay buffer 204 where the delay is controlled by selectively connecting capacitive loads 222 responsive to the low-order bits of a count in counter 224. The clock signal then enters delay line 206, where its delay is further adjusted by passing through an adjustable number of delay elements 210, set by the high-order bits of the same counter. Decoders 215-1, . . . 215-n select which one of delay elements 210-1, . . . 210-n admits buffered clock signal 208 into the delay line.
The Kuge patent further controls the delay of each delay element 210 by varying its supply voltage on node 255, so that a fairly small number of delay elements will suffice. At circuit startup, DLL control circuit 250 enables reference potential generating circuit 212 to adjust the supply voltage of the delay line, responsive to the output signal 240 until the remaining adjustment is within a predetermined range. Then the DLL control circuit uses gates 252 and 254 to disable voltage supply variation and enable delay line variation to further adjust DLL delay.
The Kuge patent has the disadvantage of using analog voltage controls for initial steps toward lock, causing speed of locking to be less than optimal. As is known to one skilled in the art, supply voltage controls must operate more slowly than digital controls, to avoid underdamped oscillations (ringing). This approach gives a wide frequency range with a small number of delay line elements, but will have a slow initial lock.
The Kuge patent has the further disadvantage of having variable size delay steps in its delay line, while the delay steps in its delay buffer are a fixed size. With both the delay buffer and delay line driven from the same counter, each counter change needs to change the total delay of both stages in a uniform fashion to be able to smoothly adjust the total delay. This is impossible since the delay of each delay line element changes with node 255 voltage, while the delay of the delay buffer step does not change. This problem will cause the DLL to have a variable locking resolution. The total delay will not change in a uniform manner as the counter is incremented and decremented.
For example, when the low-order three bits of the counter contain all ones, then all seven units of capacitance in the delay buffer are switched on. When the counter increments, the capacitances are all switched out of the circuit, and one delay-line increment is added to the total delay. The delay-line increment should equal eight of the buffer capacitance units, but the delay-line increments vary significantly due to the voltage controls. When the delay line increment is less than seven of the buffer capacitance units, and the count increments across the boundary between the buffer and the delay line to call for more delay, the line delay decreases instead of increasing. When the delay line increment is more than eight of the buffer capacitance units, and the count crosses the boundary between the delay buffer and the delay line there is a large change in total delay. A gap appears every eighth count, at this boundary, in total delay values which the delay line can provide, due to the variable-voltage controls.
Large temperature variations are common between quiescent conditions and full speed operation. Temperature variations cause changes in circuit delay, requiring the DLL to make small delay adjustments after the initial lock. The margin between external clock and the DQ as the temperature varies will be larger than other prior art, and the current invention, because the total delay of the delay buffer and delay line do not increment in a uniform manner over temperature changes.